1. Field of the Invention
The present invention relates to a semiconductor device and its refresh method and more particularly to a semiconductor device with a plurality of banks and its refresh method.
2. Description of the Related Art
Generally, in a semiconductor device, such as a DRAM, which has a large memory capacity, a memory array is often divided into a plurality of banks (that is, blocks). In a device of this type, the respective banks are arranged in row (X) and column (Y) directions and have each a plurality of memory mats each of which includes a plurality of memory cells. In addition, X and Y decoders are placed in each bank. The X decoder is used to select a word line while the Y decoder is used to select a bit line. Further, each of the bit lines is connected to a sense amplifier via memory cells in the memory mat.
The latest DRAM often adopts a structure of arranging a single sense amplifier for the plurality of memory cells in order to connect the sense amplifier to the bit line. As a system for connecting the plurality of memory cells to the single sense amplifier, an open bit line system and a folded bit line system have been proposed. The open bit line system allows chip size reduction and hence is more frequently adopted than the folded bit line system.
In the device of the open bit line system, since a pair of bit lines connected to each of the sense amplifiers are drawn out from memory cells within mutually adjacent memory mats, the word line of the memory cell in each memory mat intersects only a single bit line. Thus, the open bit line system is sometimes called a one-intersection system.
On the other hand, in the DRAM which has memory arrays each of which is divided into the plurality of banks, a refreshing operation is usually performed simultaneously in connection with the plurality of banks. Problems peculiar to the refreshing operation in the DRAM with the plurality of banks and their solving means are described in Japanese Unexamined Patent Application Publication No. 2004-55005.
Specifically, Japanese Unexamined Patent Application Publication No. 2004-55005 points outs that in a case that the open bit line system is adopted in the DRAM in which the memory array is divided into the plurality of banks, the current required to refresh an end memory mat (hereinafter, referred to as an end mat) disposed at an end of each bank becomes larger than that required to refresh a normal memory mat disposed in a position other than the end.
In Japanese Unexamined Patent Application Publication No. 2004-55005, the current required for refreshing end mats of each bank can be reduced by changing address allocation to a row selection line of each memory mat for each bank so as to avoid simultaneous activation of end mats in two or more banks upon refreshing the end mat. That is, in Japanese Unexamined Patent Application Publication No. 2004-55005, in order to change address allocation to the row selection line, the wiring layout of the X decoder is changed for each bank.
On the other hand, in order to cope with an increase in memory capacity, a semiconductor device, such as a DRAM, usually has a redundancy circuit which includes spare cells (redundant cells) and which is arranged, for example, for each word line, in preparation for generation of a defective cell. In this event, the defective cell is replaced with the redundant cell included in the redundancy circuit upon generation of the defective cell.
Japanese Unexamined Patent Application Publication No. 2004-55005 refers only to the refresh operation performed when the memory mat normally operates and does not describe the case where a defective bit line is generated in a memory mat and the memory mat concerned is replaced with a redundancy circuit.